Description
Ogma is the modular flight computer I lead for the University of Limerick Aeronautics Society, built for a student high-powered rocket targeting roughly 9km altitude.
It's split across five four-layer PCBs connected over CAN: Croí handles flight state, sensors, and logging; Teachtaire does LoRa and GNSS; Foinse handles power; Lámh drives the airbrakes; Pléasc handles recovery deployment. A separate groundstation receives telemetry on the ground.
The stack is designed to slide into a rail mount system in the avionics bay.
Progress
I designed the architecture and lead a team of five. I specced the common power, CAN, and board interfaces, ran KiCad onboarding sessions, and ran routing sessions where we laid out boards together at a projector. I also handled the BOM, Gerber review, manufacturing, and our JLCPCB sponsorship.
I hand-stencilled the solder paste and placed every component for Rev 1, then spent a long time hand-bodging the assembled boards into working hardware. We currently have two Croí, two Foinse, and two Teachtaire boards complete; one Lámh and one Pléasc are nearly complete, pending the correct optocouplers. It worked, but the time cost was totally unreasonable. Rev 2 will be ordered as fully assembled PCBAs.
Rev 1 worked, but it was harder to debug than it could have been. Croí needed SWD signal damping, SPI bodges, and a repaired power path. Foinse had a dead battery-ORing path that was hidden by an alternate power input covering for it. Lámh had a broken RTOS tick integration, and taught us that a servo can report successful I2C writes while still receiving no power or PWM at all downstream. Teachtaire forced us to stop being vague about the actual fitted radio module, UART handling, and packet format — all three had drifted from what the docs claimed.
To make bring-up faster next time, we wrote bare peripheral probes and a Python console that identifies, flashes, and diagnoses each board over SWD. Croí can stream live status over SRAM, retrieve append-only flash logs, and plot them locally. The stack now shares pinned CAN contracts, and actuator and recovery commands use explicit leases and defined safe states.
Current firmware builds across the whole stack and software tests pass. Hardware-in-the-loop testing, calibration, and full flight rehearsal are still underway. The next target is to fly the stack in an L1 launch around mid-August.
Documentation
Repos: Croí, Teachtaire, Foinse, Lámh, Pléasc, Groundstation.
Reddit reviews: initial review, Rev 1.2 final review.